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1 isl54222a high-speed usb 2.0 (480mbps) multiplexer isl54222a the intersil isl54222a is a single supply dual 2:1 multiplexer that can operate from a single 1.8v to 3.3v supply. it contains two spdt (single pole/double throw) switches configured as a dpdt. the part was designed for switching or routing of usb high-speed signals and/or usb full-spe ed signals in portable battery powered products. the 4.4 switches can swing rail-to-rail and were specifically designed to pass usb full speed data signals that range from 0v to 3.3v and usb high-speed data signals that range from 0v to 400mv with a single supply as low as 1.8v. they have high bandwidth and low capacitance to pass usb high speed data signals with minimal distortion. the digital logic in puts are 1.8v logic compatible when operated with a 1.8v to 3.3v supply. the isl54222a has an output enable pin to open all the switches and put the part in a low power state. the isl54222a is available in 10 ld 1.8mmx1.4mm tqfn, 10 ld 2.1mmx1.6mm tqfn, 10 ld tdfn and 10 ld msop packages. it operates over a temperature range of -40 to +85c. related literature ? technical brief tb363 ?guidelines for handling and processing moisture sensitive surface mount devices (smds)? ? application note an1450 ?isl54222airueval1z evaluation board user?s manual? features ? high-speed (480mbps) and full-speed (12mbps) signaling capability per usb 2.0 ? 1.8v logic compatible ? low power all off state ? power off protection ? d-/d+ pins overvoltage tolerant to 5.5v ? -3db frequency . . . . . . . . . . . . . . . . . . 780mhz ? low on capacitance @ 240mhz . . . . . . . . . 4.2pf ? low on-resistance @ v dd = 3v . . . . . . . . 4.4 ? low on-resistance @ v dd = 1.8v . . . . . . . 5.7 ? single supply operation (v dd ) . . . . . 1.8v to 3.3v ? available in tqfn, tdfn, msop packages ? pb-free (rohs compliant) ? compliant with usb 2.0 short circuit and overvoltage requirements without additional external components ? hbm esd performance i/o to gnd . . . . . . >12kv applications* (see page 15) ? mp3 and other personal media players ? cellular/mobile phones ?pda?s ? digital cameras and camcorders ? usb switching application block diagram usb 2.0 hs eye pattern with switches in the signal path isl54222a usb transceiver high-speed usb connector d- d+ sel gnd hsd1- hsd1+ hsd2- hsd2+ v dd oe logic controller usb transceiver full-speed vbus d- d+ gnd or full-speed high_speed or portable media device time scale (0.2ns/div) voltage scale (0.1v/div) caution: these devices are sensitive to electrostatic discharge; follow proper ic handling procedures. 1-888-intersil or 1-888-468-3774 | intersil (and design) is a registered trademark of intersil americas inc. copyright intersil americas inc. 2009, 2010. all rights reserved all other trademarks mentioned are the property of their respective owners. february 4, 2010 fn6902.1
2 fn6902.1 february 4, 2010 pin configurations isl54222a (10 ld 1.8x1.4 tqfn) top view isl54222a (10 ld 2.1x1.6 tqfn) top view isl54222a (10 ld 3x3 tdfn) top view isl54222a (10 ld msop) top view note: 1. switches shown for sel = logic ?1? and oe = logic ?0?. 8 10 d- oe d+ vdd 9 7 2 3 4 gnd hsd1+ hsd2+ 5 sel logic control 1 6 hsd1- hsd2- 1 3 4 oe hsd2+ hsd2- hsd1+ vdd 2 10 5 7 8 hsd1- d+ d- gnd 9 6 sel logic control sel hsd1+ d+ hsd2+ hsd1- gnd 1 2 3 4 5 10 9 8 7 6 d- hsd2- vdd oe logic control pd sel hsd1+ d+ hsd2+ hsd1- gnd 1 2 3 4 5 10 9 8 7 6 d- hsd2- vdd oe logic control truth table oe sel hsd1-, hsd1+ hsd2-, hsd2+ 0 0 on off 01 off on 1x off off note: logic ?0? when 0.5v, logic ?1? when 1.4v with a 1.8v to 3.3v supply. pin descriptions tdfn msop tqfn 1.8x1.4 tqfn 2.1x1.6 name function 10 10 9 10 vdd power supply (1.8v to 3.3v) 1 1 10 1 sel select logic control input 22 1 2hsd1 + usb data port (channel 1 positive input) 33 2 3hsd2 + usb data port (channel 2 positive input) 4 4 3 4 d+ usb data common positive port 5 5 4 5 gnd ground connection 6 6 5 6 d- usb data common negative port 7 7 6 7 hsd2- usb data port (channel 2 negative input) 8 8 7 8 hsd1- usb data port (channel 1 negative input) 99 8 9oe bus switch enable pd - - - pd thermal pad. tie to ground or float pin descriptions (continued) tdfn msop tqfn 1.8x1.4 tqfn 2.1x1.6 name function isl54222a
3 fn6902.1 february 4, 2010 ordering information part number (note 5) part marking temp. range (c) package (pb-free) pkg. dwg. # isl54222airuz-t (notes 2, 4) x -40 to +85 10 ld 1.8x1.4mm tqfn (tape and reel) l10.1.8x1.4a ISL54222AIRU1Z-T (notes 2, 4) gs -40 to +85 10 ld 2.1x1.6mm tqfn (tape and reel) l10.2.1x1.6a isl54222airtz (note 3) 222a -40 to +85 10 ld 3x3 tdfn l10.3x3a isl54222airtz-t (notes 2, 3) 222a -40 to +85 10 ld 3x3 tdfn (tape and reel) l10.3x3a isl54222aiuz (note 3) 4222a -40 to +85 10 ld msop m10.118 isl54222aiuz-t (notes 2, 3) 4222a -40 to +85 10 ld msop (tape and reel) m10.118 isl54222airueval1z evaluation board notes: 2. please refer to tb347 for details on reel specifications. 3. these intersil pb-free plastic packaged products employ special pb-free material sets, molding compounds/die attach materials, and 100% matte tin pl ate plus anneal (e3 termination finish, which is rohs compliant and compatible with both snpb and pb-free soldering operations). intersil pb-free products are msl classified at pb-free peak reflow temperatures that meet or exceed the pb-free requirements of ipc/jedec j std-020. 4. these intersil pb-free plastic packaged products employ special pb-free material sets; molding compounds/die attach materials and nipdau plate - e4 termination finish, which is rohs compliant and compatible with both snpb and pb-free soldering operations. intersil pb-free products are msl classified at pb-free peak reflow temperatures that meet or exceed the pb-free requirements of ipc/jedec j std-020. 5. for moisture sensitivity level (msl), please see device information page for isl54222a . for more information on msl please see techbrief tb363 . isl54222a
4 fn6902.1 february 4, 2010 absolute maximum ratings thermal information v dd to gnd . . . . . . . . . . . . . . . . . . . . . . . . . -0.3v to 3.5v input voltages hsd2x, hsd1x (note 6) . . . . . . . . . . . . . . . . - 0.3v to 6v sel, oe (note 6) . . . . . . . . . . . . . -0.3 to ((v dd ) + 0.3v) output voltages d+, d- (note 6) . . . . . . . . . . . . . . . . . . . . . -0.3v to 6v continuous current (hsd2x, hsd1x) . . . . . . . . . . . 40ma peak current (hsd2x, hsd1x) (pulsed 1ms, 10% duty cycle, max) . . . . . . . . . 100ma esd rating: human body model . . . . . . . . . . . . . . . . . . . . . . . . >8kv human body model, (i/o pins to gnd). . . . . . . . . . >12kv machine model . . . . . . . . . . . . . . . . . . . . . . . . . . >500v charged device model . . . . . . . . . . . . . . . . . . . . . >2.2kv latch-up tested per jedec; clas s ii level a . . . . . at +85c thermal resistance (typical) ja (c/w) jc (c/w) 10 ld tdfn (notes 8, 9) . . . . . . . . 55 18 10 ld msop (notes 7, 10) . . . . . . . 165 65 10 ld 2.1x1.6 tqfn (notes 7, 10) 160 100 10 ld 1.8x1.4 tqfn (notes 7, 10) 160 105 maximum junction temperature (plastic package). . +150c maximum storage temperature range. . . . . -65c to +150c pb-free reflow profile . . . . . . . . . . . . . . . . . .see link below http://www.intersil.com/pbfree/pb-freereflow.asp operating conditions temperature range . . . . . . . . . . . . . . . . . . -40c to +85c v dd supply voltage range . . . . . . . . . . . . . . . 1.8v to 3.3v logic control input voltage . . . . . . . . . . . . . . . . 0v to v dd analog signal range . . . . . . . . . . . . . . . . . . . . . 0v to 3.3v caution: do not operate at or near the maximum ratings listed for extended periods of time. exposure to such conditions may adv ersely impact product reliability and result in failures not covered by warranty. notes: 6. signals on hsd1x, hsd2x, d+,d- exceeding gnd by specified amount are clamped. signals on oe and sel exceeding v dd or gnd by specified amount ar e clamped. limit current to maximum current ratings. 7. ja is measured with the component mounted on a high effective thermal conductivity test board in free air. see tech brief tb379 for details. 8. ja is measured in free air with the component mounted on a high effective thermal conductivity test board with ?direct attach? features. see tech brief tb379. 9. for jc , the ?case temp? location is the center of the exposed metal pad on the package underside. 10. for jc , the ?case temp? location is taken at the package top center. electrical specifications - 1.8v to 3.3v supply test conditions: v dd = +3.3v, gnd = 0v, v sel h = 1.4v, v sel l = 0.5v, v oe h =1.4v, v oe l = 0.5v, (note 11), unless otherwise specified. boldface limits apply over the operating temperature range, -40c to +85c. parameter test conditions temp (c) min (notes 12, 13) typ max (notes 12, 13) units analog switch characteristics on-resistance, r on (high- speed) v dd = 1.8v, sel = 0.5v or 1.4v, oe = 0.5v, i dx = 40ma, v hsd1x or v hsd2 x = 0v to 400mv (see figure 3, note 16) 25 - 5.7 8 full - - 10 r on matching between channels, r on (high-speed) v dd = 1.8v, sel = 0.5v or 1.4v, oe = 0.5v, i dx = 40ma, v hsd1x or v hsd2 x = voltage at max r on , (notes 15, 16) 25 - 0.072 0.5 full - - 0.55 r on flatness, r flat(on) (high-speed) v dd = 1.8v, sel = 0.5v or 1.4v, oe = 0.5v, i dx = 40ma, v hsd1x or v hsd2 x = 0v to 400mv, (notes 14, 16) 25 - 0.60 0.9 full - - 1 off leakage current, i hsd1x(off) v dd = 3.3v, sel = v dd and oe = 0v or oe = v dd , v dx = 0.3v, 3v, v hsd1x = 3v, 0.3v, v hsd2x = 0.3v, 3v 25 -15 0.35 15 na full -20 - 20 na on leakage current, i hsd1x(on) v dd = 3.3v, sel = oe = 0v, v dx = 0.3v, 3v, v hsd1x =0.3v, 3v, v hsd2x = 3v, 0.3v 25 -20 5 20 na full -25 - 25 na off leakage current, i hsd2x(off) v dd = 3.3v, sel = oe = 0v or oe = v dd , v dx = 3v, 0.3v, v hsd2x = 0.3v, 3v, v hsd1x = 3v, 0.3v 25 -15 0.26 15 na full -20 - 20 na isl54222a
5 fn6902.1 february 4, 2010 on leakage current, i hsd2x(on) v dd = 3.3v, sel = v dd , oe = 0v, v dx = 0.3v, 3v, v hsd2x =0.3v, 3v, v hsd1x = 3v, 0.3v 25 -20 4.4 20 na full -25 - 25 na power off leakage current, i off v dd = 0v, v d+ = 0v to 5.25v, v d- = 0v to 5.25v 25 - 0.008 0.025 a full - - 0.65 a dynamic characteristics turn- on ti me , t on v dd = 3.3v, v input = 3v, r l = 500 , c l = 50pf (figure 1) 25 - 25 - ns turn-off time, t off v dd = 3.3v, v input = 3v, r l = 500 , c l = 50pf (figure 1) 25 - 17 - ns break-before-make time delay, t d v dd = 3.3v, v input = 3v, r l = 500 , c l = 50pf (figure 2) 25 - 17 - ns turn- on e nabl e ti me , t enable v dd = 3.3v, v input = 3v, r l = 15k , c l = 50pf, time out of all-off state 25 - 37 - ns turn-off disable time, t disable v dd = 3.3v, v input = 3v, r l = 15k , c l = 50pf, time into all-off state, time is highly dependent on the load (r l ,c l ) time constant. 25 - 96 - ns skew, (t skewout - t skewin ) v dd = 3.3v, sel = 0v or 3.3v, oe = 0v, r l = 45 , c l = 10pf, t r = t f = 500ps at 480mbps, (duty cycle = 50%) (figure 6) 25 - 50 - ps rise/fall de gradation (propagation delay), t pd v dd = 3.3v, sel = 0v or 3.3v, oe = 0v, r l = 45 , c l = 10pf, ( figure 6) 25 - 250 - ps crosstalk v dd = 3.3v, r l = 50 , f = 240mhz (see figure 5) 25 - -31 - db off-isolation v dd = 3.3v, oe = 3.3v, r l = 50 , f = 240mhz 25 - -28 - db -3db bandwidth signal = 0dbm, 0.2vdc offset, r l = 50 25 - 780 - mhz off capacitance, c hsxoff f = 1mhz, v dd = 3.3v, sel = 0v, oe = 3.3v, v hsd1x or v hsd2x = v dx = 0v (figure 4) 25 - 2.6 - pf com on capacitance, c dx(on) f = 1mhz, v dd = 3.3v, sel = 0v or 3.3v, oe = 0v, v hsd1x or v hsd2x = v dx = 0v (figure 4) 25 - 6.7 - pf com on capacitance, c dx(on) f = 240mhz, v dd = 3.3v, sel = 0v or 3.3v, oe = 0v, v hsd1x or v hsd2x = v dx = 0v (figure 4) 25 - 4.2 - pf power supply characteristics power supply range, v dd full 1.8 3.3 v positive supply current, i dd v dd = 3.3v, sel = 0v or v dd , oe = 0v 25 - 32 43 a full - - 50 a positive supply current, i dd (low power state) v dd = 3.3v, sel = 0v or v dd , oe = v dd 25 - 0.77 1 a full - - 1.5 a electrical specifications - 1.8v to 3.3v supply test conditions: v dd = +3.3v, gnd = 0v, v sel h = 1.4v, v sel l = 0.5v, v oe h =1.4v, v oe l = 0.5v, (note 11), unless otherwise specified. boldface limits apply over the operating temperature range, -40c to +85c. (continued) parameter test conditions temp (c) min (notes 12, 13) typ max (notes 12, 13) units isl54222a
6 fn6902.1 february 4, 2010 positive supply current, i dd v dd = 1.8v, sel = 0v, oe = 0v 25 - 5.8 7.8 a full - - 8.3 a positive supply current, i dd (low power state) v dd = 1.8v, sel = 0v, oe = v dd 25 - 0.12 0.3 a full - - 1 a digital input characteristics input voltage low, v sell , v oe l v dd = 1.8v to 3.3v full - - 0.5 v input voltage high, v selh , v oe h v dd = 1.8v to 3.3v full 1.4 - v dd v input current, i sell , i oe l v dd = 3.3v, sel = 0v, oe = 0v full - 170 - na input current, i selh v dd = 3.3v, sel = 3.3v full - -1.4 - na input current, i oe h v dd = 3.3v, oe = 3.3v full - -1.4 - na notes: 11. v logic = input voltage to perform proper function. 12. the algebraic convention, whereby the most negative value is a minimum and the most positive a maximum, is used in this data sheet. 13. parameters with min and/or max limits are 100% tested at + 25c, unless otherwise specified. temperature limits established by characterization and are not production tested. 14. flatness is defined as the di fference between maximum and minimum value of on-resistance over the specified analog signal range. 15. r on matching between channels is calculated by subtracting the channel with the highest max r on value from the channel with lowest max r on value, between hsd2+ and hsd2- or between hsd1+ and hsd1-. 16. limits established by characterization and are not production tested. electrical specifications - 1.8v to 3.3v supply test conditions: v dd = +3.3v, gnd = 0v, v sel h = 1.4v, v sel l = 0.5v, v oe h =1.4v, v oe l = 0.5v, (note 11), unless otherwise specified. boldface limits apply over the operating temperature range, -40c to +85c. (continued) parameter test conditions temp (c) min (notes 12, 13) typ max (notes 12, 13) units test circuits and waveforms logic input waveform is inverted for switches that have the opposite logic sense. figure 1a. measurement points repeat test for all switches. c l includes fixture and stray capacitance. figure 1b. test circuit figure 1. switching times 50% t r < 20ns t f < 20ns t off 90% v dd 0v v input 0v t on logic input switch input switch output 90% v out v out v (input) r l r l r on + ----------------------- - = switch input v in v out r l c l dx hsdxx sel 500 50pf gnd v dd c oe v input isl54222a
7 fn6902.1 february 4, 2010 figure 2a. measurement points repeat test for all switches. c l includes fixt ure and stray capacitance. figure 2b. test circuit figure 2. break-before-make time figure 3. r on test circuit test circuits and waveforms (continued) 10% v dd 0v t d logic input switch output 0v v out v in sel dx r l c l v out 50pf 500 hsd2x v dd gnd v input c oe hsd1x v dd c ov or vdd hsdx dx sel gnd v hsdx v 1 r on = v 1 /40ma 40ma repeat test for all switches. oe isl54222a
8 fn6902.1 february 4, 2010 figure 4. capacitance test circuit figure 5. crosstalk test circuit figure 6a. measurement points figure 6b. test circuit figure 6. skew test test circuits and waveforms (continued) v dd c gnd hsdxx dx sel impedance analyzer 0v or repeat test for all switches. oe v dd analyzer v dd c hsd1x signal generator r l gnd sel dx 50 nc dx hsd2x signal direction through switch is reversed, worst case values are recorded. repeat test for all switches. oe v in din+ din- out+ out- 50% 50% 90% 10% 10% 10% 10% 90% 90% 50% 90% 50% t ri t fi t ro t f0 t skew_i t skew_o out+ c l comd1 d2 gnd v dd c d1 comd2 c l out- din+ din- |tro - tri| delay due to switch for rising input and rising output signals. |tfo - tfi| delay due to switch for fa lling input and falling output signals. |tskew_0| change in skew through the switch for output signals. |tskew_i| change in skew through the switch for input signals. 15.8 15.8 143 143 45 45 sel v in oe isl54222a
9 fn6902.1 february 4, 2010 application block diagram detailed description the isl54222a device is a dual single pole/double throw (spdt) analog switch configured as a dpdt that operates from a single dc power supply in the range of 1.8v to 3.3v. it was designed to function as a dual 2-to-1 multiplexer to select between two usb high-speed differential data signals in portable battery powered products. it is offered in msop, tdfn and small tqfn packages for use in mp3 players, cameras, pdas, cell phones, and other personal media players. the part consists of four 4.4 high-speed (hsx) switches. these switches have high bandwidth and low capacitance to pass usb high-speed (480mbps) differential data signals with minimal edge and phase distortion. they can also swin g from 0v to 3.3v to pass usb full speed (12mbps) differential data signals with minimal distortion. the device has an enable pin to open all switches and put the part in a low power down state. it can be used to facilitate proper bus disconnect and connection when switching between the usb sources. the isl54222a was designed for mp3 players, cameras, cell phones, and other personal media player applications that have multiple high-speed or full-speed transceivers sections and need to multiplex between these usb sources to a single usb host (computer). a typical application block diagram of this functionality is shown on page 9. a detailed description of the hs switches is provided in the following section. high-speed (hsx) switches the hsx switches (hsd1-, hsd1+, hsd2-, hsd2+) are bi-directional switches that can pass 0v to 3.3v signals. when powered with a 1.8v supply, these switches have a nominal r on of 5.7 over the signal range of 0v to 400mv with a r on flatness of 0.60 . the r on matching between the hsd1 and hsd2 switches over this signal range is only 0.072 , ensuring minimal impact by the switches to usb high-speed signal transitions. as the signal level increases, the r on switch resistance increases. with supply of 1.8v, the switch resistance with the signal level at the rail is nominally 12 . see figures 7, 8, 9, 10, 11 and 12 in the ?typical performance curv es? beginning on page 11. the hsx switches were specifically designed to pass usb 2.0 high-speed (480mbps) differential signals in the range of 0v to 400mv. they have low capacitance (4.2pf) and high bandwidth to pass the usb high-speed signals with minimum edge and phase dist ortion to meet usb 2.0 high-speed signal quality specifications. see figure 13 in the ?typical performance curves? on page 12 for usb high-speed eye pattern take n with switches in the differential signal paths. the hsx switches can also pass usb full-speed signals (12mbps) with minimal distortion and meet all the usb requirements for usb 2.0 fu ll-speed signaling. see figures 14 and 15 in the ?typical performance curves? on page 13 for usb full-speed eye patterns taken with switches in the differ ential signal paths. the maximum normal operating signal range for the hsx switches is from 0v to 3.3v. the signal voltage should not be allowed to exceed 3.3v or go below ground by more than -0 .3v for normal operation. however, in the event that the usb 5.25v v bus voltage gets shorted to one or bo th of the d-/d+ pins, the isl54222a has special faul t protection circuitry to prevent damage to the is l54222a part. the fault circuitry allows the signal pi ns (d-, d+, hsd1-, hsd1+, hsd2-, hsd2+) to be driven up to 5.5v while the v dd supply voltage is in the range of 0v to 3.3v. in this condition, the part draws < 300a of i dd current and causes no stress to the ic. in addition, when v dd is at 0v (ground) all switches are off and the fault voltage is isolated from the other side of the switch. when v dd is portable media device isl54222a usb transceiver high-speed d- d+ sel gnd hsd1- hsd1+ hsd2- hsd2+ v dd oe logic circuitry controller usb transceiver full-speed v bus d- d+ gnd or full-speed high_speed or usb connector #1 #2 isl54222a
10 fn6902.1 february 4, 2010 in the range of 1.8v to 3.3v, the fault voltage will pass through to the output of an active switch channel. during the fault condition normal operation is not guaranteed until the fault is removed. see the following ?usb 2.0 vbus short re quirements? on page 10. the hs1 channel switches are active (turned on) whenever the sel voltage is logic?0?(low) and the oe voltage is logic?0?(low). the hs2 channel switches are active (turned on) whenever the sel voltage is logic ?1? (high) and the oe voltage is logic ?0? (low). isl54222a operation the following will discuss using the isl54222a shown in the ?application block diagram? on page 9. power the power supply connected at the vdd pin provides the dc bias voltage required by the isl54222a part for proper operation. the isl54222a can be operated with a v dd voltage in the range of 1.8v to 3.3v. a 0.01f or 0.1f decoupling capacitor should be connected from the vdd pin to ground to filter out any power supply noise from entering the part. the capacitor should be located as close to the vdd pin as possible. logic control the state of the isl54222a device is determined by the voltage at the sel pin and the oe pin. sel is only active when the oe pin is logic ?0? (low). refer to ?truth table? on page 2. the isl54222a logic pins are designed to minimize current consumption when the logic control voltage is lower than the v dd supply voltage. with v dd = 3.3v and logic pins at 1.4v, the part typically draws only 6.6a. with v dd = 1.8v and logic pins at 1.4v, the part typically draws only 0.2a. driving the logic pins to the v dd supply rail minimizes power consumption. the logic pins must be driven high or low and must not float. logic control voltage levels with v dd supply voltage in the range of 1.8v to 3.3v the logic levels are: oe = logic ?0? (low) when v oe 0.5v oe = logic ?1? (high) when v oe 1.4v sel = logic ?0? (low) when v sel 0.5v sel = logic ?1? (high) when v sel 1.4v hsd1 usb channel if the sel pin = logic ?0? and the oe pin = logic ?0?, high-speed channel 1 will be on. the hsd1- and hsd1+ switches are on and the hsd2- and hsd2+ switches are off (high impedance). when a computer or usb hub is plugged into the common usb connector and channel 1 is active, a link will be established between the usb 1 transceiver section of the media player and the computer. the device transceiver 1 will be able to transmit and receive data from the computer. hsd2 usb channel if the sel pin = logic ?1? and the oe pin = logic ?0?, high-speed channel 2 will be on. the hsd2- and hsd2+ switches are on and the hs d1- and hsd1+ switches are off (high impedance). when a usb cable from a computer or usb hub is connected at the common usb connector and the part has channel 2 active, a link will be established between the usb 2 transceiver section of the media player and the computer. the device transceiver 2 will be able to transmit and receive data from the computer. all switches off/low power mode if the sel pin = logic ?0? or logic ?1? and the oe pin = logic ?1?, all of the switches will turn off (high impedance) and the part wi ll be put in a low power mode. in this mode the part draws only 1.5a (max) of current across the oper ating temperature range. the all off state can be used to switch between the two usb sections of the media player. when disconnecting from one usb device to the other usb device, you can momentarily put the isl54222a switch in the ?all off? state in order to get the computer to disconnect from the one device so it can properly connect to the other usb device when that channel is turned on. usb 2.0 v bus short requirements the usb 2.0 specification in chapter 7, section 7.1.1 states a usb device must be able to withstand a v bus short to the d+ or d- signal lines when the device is either powered off or powered on for at least 24 hours. the isl54222a part has special fault protection circuitry to meet these short circuit requirements. the fault protection circuitry allows the signal pins (d-, d+, hsd1-, hsd1+, hsd2-, hsd2+) to be driven up to 5.5v while the v dd supply voltage is in the range of 0v to 3.3v. in this overvolt age condition, the part draws < 300a of i dd current and causes no stress or damage to the ic. in addition, when v dd is at 0v (ground), all switches are off and the shorted v bus voltage is isolated from the other side of the switch. when v dd is in the range of 1.8v to 3.3v, the shorted v bus voltage will pass through to the output of an active (turned on) switch channel but not through a turned off channel. any components connected on the active channel must be able to withstand the overvoltage condition. note: during the fault condition, normal operation of the usb channel is not guaranteed until the fault condition is removed. isl54222a
11 fn6902.1 february 4, 2010 typical performance curves t a = +25c, unless ot herwise specified figure 7. on-resistance vs supply voltage vs switch voltage figure 8. on-resistance vs supply voltage vs switch voltage figure 9. on-resistance vs switch voltage figure 10. on-resistance vs switch voltage figure 11. on-resistance vs switch voltage figure 12. on-resistance vs switch voltage r on ( ) v com (v) 3.0 3.5 4.0 4.5 5.0 5.5 6.0 0 0.1 0.2 0.3 0.4 1.8v 2.7v 3.3v 3.0v i com = 40ma 2 4 6 8 10 12 14 0 0.5 1.0 1.5 2.0 2.5 3.0 3.3 r on ( ) v com (v) 1.8v 2.7v 3.0v 3.3v i com = 1ma 2 3 4 5 6 7 8 0 0.1 0.2 0.3 0.4 r on ( ) v com (v) +25c +85c -40c i com = 40ma v+ = 1.8v 0 2 4 6 8 10 12 14 16 0 0.2 0.4 0.6 0.8 1.0 1.2 1.4 1.6 1.8 r on ( ) v com (v) +25c +85c -40c i com = 1ma v+ = 1.8v 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 00.10.20.30.4 r on ( ) v com (v) i com = 40ma +25c +85c -40c v+ = 3.3v 0 1 2 3 4 5 6 7 8 9 0 0.5 1.0 1.5 2.0 2.5 3.0 3.3 r on ( ) v com (v) +25c +85c -40c i com = 1ma v+ = 3.3v isl54222a
12 fn6902.1 february 4, 2010 figure 13. eye pattern: 480mbps with usb switches in the signal path typical performance curves t a = +25c, unless ot herwise specified (continued) time scale (0.2ns/div) voltage scale (0.1v/div) v dd = 1.8v isl54222a
13 fn6902.1 february 4, 2010 figure 14. eye pattern: 12mbps with usb switches in the signal path figure 15. eye pattern: 12mbps with usb switches in the signal path typical performance curves t a = +25c, unless ot herwise specified (continued) time scale (10ns/div) voltage scale (0.5v/div) v dd = 1.8v time scale (10ns/div) voltage scale (0.5v/div) v dd = 3.3v isl54222a
14 fn6902.1 february 4, 2010 figure 16. frequency response figure 17. off-isolation figure 18. crosstalk die characteristics substrate and tdfn thermal pad potential (powered up): gnd transistor count: 325 process: submicron cmos typical performance curves t a = +25c, unless ot herwise specified (continued) -4 -3 -2 -1 0 1 frequency (hz) normalized gain (db) 1m 10m 100m 1g v in = 0dbm, 0.2vdc bias r l = 50 -110 -100 -90 -80 -70 -60 -50 -40 -30 -20 -10 0.001m 0.01m 0.1m 1m 10m 100m 500m frequency (hz) normalized gain (db) v in = 0dbm, 0.2vdc bias r l = 50 0.001m 0.01m 0.1m 1m 10m 100m 500m frequency (hz) normalized gain (db) -110 -100 -90 -80 -70 -60 -50 -40 -30 -20 isl54222a
15 fn6902.1 february 4, 2010 products intersil corporation is a leader in the design and manuf acture of high-performance analog semiconductors. the company's products address some of the industry's fastest growing markets, such as, flat panel displays, cell phones, handheld products, and notebooks. intersil's product families address power management and analog signal processing functions. go to www.intersil.com/products for a complete list of intersil product families. *for a complete listing of applications, related documentat ion and related parts, please see the respective device information page on intersil.com: isl54222a to report errors or suggestions for this datasheet, please go to www.intersil.com/askourstaff fits are available from our website at http://rel.intersil.com/reports/search.php revision history the revision history provided is for informat ional purposes only and is believed to be accurate, but not warranted. please go t o web to make sure you have the latest rev. date revision change 2/4/10 fn6902.1 updated to new intersil data sheet format. page 1 updated with related lite rature and marketing graphics. added to pin configurations 10 ld msop. updated pin description table by adding column s reflecting package option, pin names and functions. updated ordering info rmation by numbering all notes and adding msl note, now a new standard. added latchup to abs max ratings added to thermal resistance 10 ld 1.8x1.4 utqf n tja 160 and tjc of 105 with corresponding notes added to thermal resistance tjc of 100 and corresponding note for msop package changed tja for 10 ld 2.1x1.6 utqfn from 155 to 160. added tjc and corresponding note. updated package outline drawings l10.1.8x1.4a and l10.3x3a to most recent revisions. changes to l10.1.8x1.4a were to add solder f ootprint. changes to l10. 3x3a were to change tolerance in top view from 0.15 to 0.10. page 1 in features section ch anged "low on capacitance 6.7pf" to "low on capacitance @ 240mhz 4.2pf" page 1 in features section changed "low on resistance 5.7ohms" to "low on resistance @ 1.8v 5.7ohms" added in features section "low on resistance @ vdd = 3v 4.4ohms" electrical specification table: ad ded com on capacitance at 240mhz 5/13/09 fn6902.0 initial release. isl54222a
16 fn6902.1 february 4, 2010 isl54222a thin dual flat no-lead plastic package (tdfn) // nx (b) section "c-c" for odd terminal/side e cc 5 c l terminal tip (a1) bottom view a 6 area index c c 0.10 0.08 side view 0.10 2x e a b c 0.10 d top view cb 2x 6 8 area index nx l e2 e2/2 ref. e n (nd-1)xe (datum a) (datum b) 5 0.10 8 7 d2 b a c n-1 12 plane seating c a a3 nx b d2/2 nx k l1 9 l m l10.3x3a 10 lead thin dual flat no-lead plastic package symbol millimeters notes min nominal max a 0.70 0.75 0.80 - a1 - - 0.05 - a3 0.20 ref - b 0.20 0.25 0.30 5, 8 d 2.95 3.0 3.05 - d2 2.25 2.30 2.35 7, 8 e 2.95 3.0 3.05 - e2 1.45 1.50 1.55 7, 8 e 0.50 bsc - k 0.25 - - - l 0.25 0.30 0.35 8 n 10 2 nd 5 3 rev. 4 8/09 notes: 1. dimensioning and tolerancing conform to asme y14.5-1994. 2. n is the number of terminals. 3. nd refers to the number of terminals on d. 4. all dimensions are in millim eters. angles are in degrees. 5. dimension b applies to the metallized terminal and is measured between 0.15mm and 0.30mm from the terminal tip. 6. the configuration of the pin #1 identifier is optional, but must be located within the zone indicated. the pin #1 identifier may be either a mold or mark feature. 7. dimensions d2 and e2 are fo r the exposed pads which provide improved electrical and thermal performance. 8. nominal dimensions are provided to assist with pcb land pattern design efforts, see intersil technical brief tb389. 9. compliant to jedec mo-229-weed-3 except for d2 dimensions. ( 2.90 ) (1.50) ( 10x 0.25) ( 10x 0.50) ( 2.30 ) ( 2.00 ) typical recommended land pattern (8x 0.50) pin 1
17 fn6902.1 february 4, 2010 isl54222a package outline drawing l10.1.8x1.4a 10 lead ultra thin quad flat no-lead plastic package rev 4, 9/09 nd and ne refer to the number of terminals on d (4) and e (6) side, dimension b applies to the meta llized terminal and is measured the configuration of the pin #1 identifier is optional, but must be all dimensions are in millimet ers. tolerances 0.05mm unless n is the number of terminals. total 10 leads. 6. 3. 5. 4. 2. dimensioning and tolerancing conform to asme y14.5-1994. 1. notes: bottom view detail "x" side view typical recommended land pattern top view 6 b 1.40 a 1.80 0.10 c 2x index area 0.10 c 2x 2 1 2 1 0.50 nx 0.40 5 7 pin #1 id (datum a) (datum b) 0.10 m c a b 0.05 m c nx 0.20 10x 5 0.40 bsc c 0.05 c 0.5 0.10 c 0.05 max seating plane nx (0.20) section "c-c" e cc 5 c l terminal tip (0.05 max) 0.40 0.127 ref 0.40 0.40 bsc 0.50 0.20 0.40 1.80 0.40 0.20 2.20 1.00 0.60 1.00 land pattern 10 respectively. between 0.15mm and 0.30mm from the terminal tip. located within the zone indicated. the pin #1 identifier may be either a mold or mark feature. maximum package warpage is 0.05mm. 7. maximum allowable burrs is 0.076mm in all directions. 8. jedec reference mo-255. 9. for additional information, to assist with the pcb land pattern 10. design effort, see intersil technical brief tb389. otherwise noted. angles are in degrees.
18 fn6902.1 february 4, 2010 ultra thin quad flat no-lead plastic package (utqfn) 6 b e a d 0.10 c 2x 2 0.10 m c a b 0.05 m c (nd-1) x e c 0.05 c a 0.10 c a1 seating plane e index area pin #1 id 3 5 (datum a) (datum b) n-1 1 n nx l nx b 2 1 n top view bottom view side view nx (b) section "c-c" for odd terminal/side e cc 5 c l terminal tip (a1) l detail ?a? pin 1 id l 0.05 min 0.10 min 0.10 c 2x 4xk b l10.2.1x1.6a 10 lead ultra thin quad flat no-lead plastic package symbol millimeters notes min nomi- nal max a 0.45 0.50 0.55 - a1 - - 0.05 - a3 0.127 ref - b 0.15 0.20 0.25 5 d 2.05 2.10 2.15 - e 1.55 1.60 1.65 - e0.50 bsc- k 0.20 --- l 0.35 0.40 0.45 - n102 nd 4 3 ne 1 3 0- 12 4 rev. 3 6/06 notes: 1. dimensioning and tolerancing conform to asme y14.5- 1994. 2. n is the number of terminals. 3. nd and ne refer to the numb er of terminals on d and e side, respectively. 4. all dimensions are in millimet ers. angles are in degrees. 5. dimension b applies to the metallized terminal and is measured between 0.15mm and 0.30mm from the terminal tip. 6. the configuration of the pin #1 identifier is optional, but must be located within the zone indicated. the pin #1 identifier may be either a mold or mark feature. 7. maximum package warpage is 0.05mm. 8. maximum allowable burrs is 0.076mm in all directions. 9. same as jedec mo-255uabd except: no lead-pull-back, "a" min dimension = 0.45 not 0.50mm "l" max dimension = 0.45 not 0.42mm. 10. for additional information, to assist with the pcb land pattern design effort, see in tersil technical brief tb389. 2.00 0.80 1.75 0.25 0.50 0.275 2.50 land pattern 10 isl54222a
19 intersil products are manufactured, assembled and tested utilizing iso9000 qu ality systems as noted in the quality certifications found at www.intersil.com/design/quality intersil products are sold by description only. intersil corporation reserves the right to make changes in circuit design, soft ware and/or specifications at any time without notice. accordingly, th e reader is cautioned to verify that data sheets are current before placing orders. information furnished by intersil is believed to be accura te and reliable. however, no re sponsibility is assumed by inte rsil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which ma y result from its use. no licen se is granted by implication o r otherwise under any patent or patent rights of intersil or its subsidiaries. for information regarding intersil corporation and its products, see www.intersil.com fn6902.1 february 4, 2010 for additional products, see www.intersil.com/product_tree isl54222a mini small outline pl astic packages (msop) notes: 1. these package dimensions are wi thin allowable dimensions of jedec mo-187ba. 2. dimensioning and tolerancing per ansi y14.5m - 1994. 3. dimension ?d? does not include mold flash, protrusions or gate burrs and are measured at datum plane. mold flash, protrusion and gate burrs shall not exceed 0.15mm (0.006 inch) per side. 4. dimension ?e1? does not include interlead flash or protrusions and are measured at datum plane. interlead flash and protru- sions shall not exceed 0.15mm (0.006 inch) per side. 5. formed leads shall be planar wi th respect to one another within 0.10mm (.004) at seating plane. 6. ?l? is the length of terminal for soldering to a substrate. 7. ?n? is the number of terminal positions. 8. terminal numbers are shown for reference only. 9. dimension ?b? does not include dambar protrusion. allowable dam- bar protrusion shall be 0.08mm (0.003 inch) total in excess of ?b? dimension at maximum material condition. minimum space be- tween protrusion and adjacent lead is 0.07mm (0.0027 inch). 10. datums and to be determined at datum plane . 11. controlling dimension: millimeter. converted inch dimensions are for reference only l 0.25 (0.010) l1 r1 r 4x 4x gauge plane seating plane e e1 n 12 top view index area -c- -b- 0.20 (0.008) a b c seating plane 0.20 (0.008) c 0.10 (0.004) c -a- -h- side view b e d a a1 a2 -b- end view 0.20 (0.008) c d e 1 c l c a - h - -a - - b - - h - m10.118 (jedec mo-187ba) 10 lead mini small outline plastic package symbol inches millimeters notes min max min max a 0.037 0.043 0.94 1.10 - a1 0.002 0.006 0.05 0.15 - a2 0.030 0.037 0.75 0.95 - b 0.007 0.011 0.18 0.27 9 c 0.004 0.008 0.09 0.20 - d 0.116 0.120 2.95 3.05 3 e1 0.116 0.120 2.95 3.05 4 e 0.020 bsc 0.50 bsc - e 0.187 0.199 4.75 5.05 - l 0.016 0.028 0.40 0.70 6 l1 0.037 ref 0.95 ref - n10 107 r 0.003 - 0.07 - - r1 0.003 - 0.07 - - 5 o 15 o 5 o 15 o - 0 o 6 o 0 o 6 o - rev. 0 12/02

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